Analog signal processing applications often require the use of signal delay lines. Such delay lines can be categorized generally as either analog or digital in nature. A typical example of an analog delay line is that disclosed by Puckette et al. in U.S. Pat. No. 3,973,138 issued Aug. 3, 1976 which uses a bucket brigade of serially connected capacitors to provide a desired amount of time delay. Such analog delay lines are unfortunately relatively expensive, require the use of analog switches, and tend to suffer from crosstalk problems. In addition, either when used singly or when cascaded, such analog systems invariably reduce the bandwidth of the signal being processed.
A typical digital delay line is disclosed by Covington in U.S. Pat. No. 3,760,280 issued Sept. 18, 1973, in which a single analog signal channel is converted to a frequency modulated (FM) signal which in turn is delayed by means of a clocked digital shift register. The resulting delayed digital signal is then demodulated to provided a delayed analog signal. Such a digital delay system overcomes many of the problems of analog delay lines, but the bandwidth problem still remains. Since the digital signal is propagated through the shift register by means of a clock signal, it is necessary to use a very high speed shift register and clock to maintain the overall system bandwidth. Thus, according to conventional sampling signal theory, in order for the delayed output signal to have a 5 megahertz (MHz) information bandwidth with a 0.1% pulse width resolution, the shift register must be clocked at or above 10 gigahertz (GHz) (i.e., 5 MHz.times.1000.times.2).
Other workers such as Arnstein in U.S. Pat. No. 4,124,820 issued Nov. 7, 1978 have shown digital delay lines which do not make use of a clocked shift register, but instead achieve their desired delay function by applying an FM signal to a plurality of conventional digital gates arranged in cascade along with latch connected logic gates to reconstitute the FM pulses travelling through the delay circuit. Propagation delay is then adjusted by adding external timing capacitance or resistance to compensate for device variations. Although such an asynchronous delay line does not make use of a clock as in Covington, the resulting output signal is still bandwidth limited due to the low bandwidth of the individual digital gates, the use of latches to overcome propagation losses, and the use of resistors and capacitors to adjust the propagation delay.